与LCD控制器硬件相对应的是3个模块文件,分别是:LCD_interface.vhd,LCD_pixel_fifo.v以及LCD_controller_stream.v。其中LCD_controller_stream.v是顶层模块,其内部也包含了Avalon Streaming Port接口时序部分,LCD_pixel_fifo.v可通过QuartusII中的宏模块直接生成。当生成了上述3个文件后,可选择SOPC Builder中的System->Add Interface to User Logic命令打开Interface to User Logic对话框,选择总线类型为Avalon Memory Slave,因为工作于流模式的LCD控制器可看成一个存储器(FIFO类型),可通过添加DMA控制器来实现存储器(FIFO)到存储器(SDRAM)的DMA设置。下面给出LCD接口部分程序。
ENTITY LCD_interface IS
PORT(
reset :IN std_logic;
lcd_clk :IN std_logic;
Wrdata :IN std_logic_vector(17 downto 0);
hsync :OUT std_logic;
vsync :OUT std_logic;
enable :OUT std_logic;
lcd_R/L :OUT std_logic;
lcd_U/D :OUT std_logic;
sel_VGA_QVGA :OUT std_logic;
RGB :OUT std_logic_vector(17 downto 0);
end_of_picture :OUT std_logic);
END LCD_interface;
ARCHITECTURE trans OF LCD_interface IS
process(lcd_clk) begin
if(rising_edge(lcd_clk)) then
if(hcnt<400) then
hcnt<=hcnt+1;
else
hcnt<=(others=>0);
end if;
end if;
end process;--行计数器模块
process(lcd_clk) begin
if(rising_edge(lcd_clk)) then
if(hcnt=320) then
if(vcnt<262) then
vcnt<= vcnt+1;
else
vcnt<=(others=>0);
end if;
end if;
end if;
end process;--场计数器模块
process(lcd_clk) begin
if(rising_edge(lcd_clk)) then
if((hcnt>= 320+20+20 ) and (hcnt<320+20+20+40)) then
hs<=0;
else
hs<=1;
end if;
end if;
end process;--产生水平同步脉冲
process(vcnt)begin
if((vcnt>=240+6+6)and(vcnt<240+6+6+10)) then
VS<=0;
else
vs<=1;
end if;
end process;--产生场同步脉冲
process(lcd_clk) begin
if(rising_edge(lcd_clk)) then
if(hcnt<320 and vcnt<240)and(hcnt>20 and vcnt>6) then
en<=1;
else
en<=0;
end if;
end if;
end process;--产生显示使能控制信号
process(led_clk)begin
if(rising_edge(lcd_clk))then
if(hcnt<320 and vcnt<240)then
RGB<=Wdata;
else
RGB<=(others=>0);
end if;
end if;
end process;--像素输出及消隐
process(lcd_clk)begin
if(rising_edge(lcd_clk))then
if((vcnt=320+1)and(hcnt=0))then
end_of_picture<=1;
else
end_of_picture<=0;
end if;
end if;
end process;--一帧传输完毕
END ARCHITECTURE trans;