CD40174 CD40175中文资料

CD40174/CC40174由六个相同的D型触发器组成（CD40175/CC40175由四个相同的D型触发器）。具有相互独立的数据输入端、公共的CP和CR输入端，在时钟上升沿数据传送到Q输出端。CR为低电平时，触发器同时复位。
  真值表功能： Inputs 输入Outputs 输出Clear Clock D Q Q (Note 1) L X X L H H ↑ H H L H ↑ L L H H H X NC NC H L X NC NC
  
   CD40174 CD40175引脚图
  CD40174引脚功能：
  3 4 6 11 13 14 数据输入端
  2 5 7 10 12 15 数据输入端
  1 消除端
  9 时钟输入端
  16 电源正
  8 接地
  Absolute Maximum Ratings 绝对最大额定值： DC Supply Voltage 直流供电电压 (VDD) ?0.5V to +18V Input Voltage输入电压 (VIN) ?0.5V to VDD +0.5 VDC Storage Temperature Range储存温度范围 (TS) ?65℃ to +150℃ Power Dissipation功耗 (PD) Dual-In-Line 普通双列封装 700 mW Small Outline 小外形封装 500 mW Lead Temperature 焊接温度(TL) Soldering, 10 seconds)（焊接10秒） 260℃
  Recommended Operating Conditions 建议操作条件： DC Supply Voltage 直流供电电压 (VDD) 3V to 15 VDC Input Voltage输入电压 (VIN) 0V to VDD VDC Operating Temperature Range工作温度范围 (TA) ?55℃ to +125℃
  DC Electrical Characteristics 直流电气特性：
  符号
  Parameter参数 Conditions 条件 -55℃25℃125℃
  单位 最小 最大 最小 典型最大最小最大IDD Quiescent Device Current静态电流 VDD=5V,VIN = VDD or VSS1.0 1.030 μA VDD=10V,VIN = VDD or VSS2.0 2.060 VDD=15V,VIN = VDD or VSS4.0 4.0120 VOL LOW Level Output Voltage 输出低电平电压 VDD=5V |IO|<1μA0.05 0.050.05 V VDD=10V0.05 0.050.05 VDD=15V0.05 0.050.05 VOH HIGH Level Output Voltage 输出高电平电压 VDD=5V |IO|<1μA 4.954.95 54.95V VDD=10V 9.959.95 109.95VDD=15V 14.9514.95 1514.95VIL LOW Level Input Voltage 输入低电平电压 VDD=5V,VO=0.5Vor4.5V1.5 1.51.5 V VDD=10V, VO = 1V or 9V3.0 3.03.0 VDD=15V,VO=1.5V or 13.5V4.0 4.04.0 VIH HIGH Level Input Voltage 输入高电平电压 VDD=5V,VO =0.5V or 4.5V 3.53.5 3.5V VDD=10V,VO=1V or 9V 7.07.0 7.0VDD=15V,VO=1.5V or 13.5V 11.011.0 11.0IOL LOW Level Output Current输出低电平电流VDD = 5V, VO = 0.4V 0.640.51 0.880.36mA VDD = 10V, VO = 0.5V 1.61.3 2.250.9VDD = 15V, VO = 1.5V 4.23.4 8.82.4IOH HIGH Level Output Current输出高电平电流VDD = 5V, VO = 4.6V ?0.64?0.51 ?0.88?0.36mA VDD = 10V, VO = 9.5V ?1.6?1.3 ?2.25?0.9VDD = 15V, VO = 13.5V ?4.2?3.4 ?8.8?2.4IIN Input Current 输入电流 VDD=15V,VIN = 0V0.1 ?10?50.1 ?1.0μA VDD=15V,VIN = 15V?0.1 10?5?0.1 1.0
  AC Electrical Characteristics 交流电气特性：
  Symbol 符号 Parameter 参数
  Conditions 条件 最小 典型 最大 Units 单位 tPHL, tPLH Propagation Delay Time to a Logical “0” or Logical “1” from Clock to Q or Q (CD40175 Only) VDD = 5V190 300 ns VDD = 10V75 110 VDD = 15V60 90 tPHL Propagation Delay Time to a
  Logical “0” from Clear to Q VDD = 5V180 300 ns VDD = 10V70 110 VDD = 15V60 90 tPLH Propagation Delay Time to a Logical
  “1” from Clear to Q (CD40175 Only) VDD = 5V230 400 ns VDD = 10V90 150 VDD = 15V75 120 tSU Time Prior to Clock Pulse that
  Data must be Present VDD = 5V45 100 ns VDD = 10V15 40 VDD = 15V13 35 tH Time after Clock Pulse that
  Data Must be Held VDD = 5V?11 0 ns VDD = 10V?4 0 VDD = 15V?3 0 tTHL, tTLH Transition Time过渡时间 VDD = 5V100 200 ns VDD = 10V50 100 VDD = 15V40 80 tWH, tWL Minimum Clock Pulse Width最小时钟脉冲宽度 VDD = 5V130 250 ns VDD = 10V45 100 VDD = 15V40 80 tWL Minimum Clear Pulse Width 最小无阻脉冲宽度
   VDD = 5V120 250 ns VDD = 10V45 100 VDD = 15V40 80 tRCL Maximum Clock Rise Time 最大时钟上升时间VDD = 5V 15 μs VDD = 10V 5.0 VDD = 15V