OverviewoftheMAX1104024-BitSimultaneous-Sampling,Sigma-Delta

Overview of the MAX11040 24-Bit Simultaneous-Sampling, Sigma-Delta ADC
  Abstract: This application note highlights the key features of the MAX11040 simultaneous-sampling sigma-delta ADC. The article will discuss 4-channel simultaneous sampling; the ability to program phase delays individually for each channel; cascading up to eight devices; and the operation of the active-low FAULT and OVERFLOW signals. Example test data, generated with device's evaluation (EV) kit, will be shown.
  
  Four-Channel Simultaneous Sampling
  The MAX11040 integrates four 24-bit, sigma-delta ADCs to enable 4-channel simultaneous sampling. Unlike multiplexed-channel sigma-delta ADCs that do not maintain phase integrity, the MAX11040 not height=335 alt="Figure 1. The same sine-wave signal was applied to the four inputs of the MAX11040. Simultaneous outputs are shown at right." src="/data/attachment/portal/201007/ET33814201007230417381.gif" width=650>
  Figure 1. The same sine-wave signal was applied to the four inputs of the MAX11040. Simultaneous outputs are shown at right.
  
  Individual Phase-Delay Programming for Each Channel
  Users can independently program phase delay for each ADC channel with a maximum of 333µs delay in 1.33µs steps. By programming phase delays into the ADC channels, the users can null out inherent phase delays caused by filters, delay lines, etc., in their signal path. The delay step size is also smaller than the data rate, thus allowing the user a resolution not available after acquisition.
  
  Figure 2 shows the sampled output when zero phase delay is programmed and when varying phase delays are programmed. In both cases, all four inputs are tied to the same signal source.
  
  
  Figure 2. The same sine-wave signal was applied to the four inputs of the MAX11040. Figure 2A shows the simultaneous output from the four channels when zero phase delay was programmed. Figure 2B shows the simultaneous output from the four channels when varying phase delays were programmed.
  
  Cascade Up to 8 Devices
  If four channels are not sufficient for an application, height=326 alt="Figure 3. Diagram of the setup for cascading up to 8 MAX11040 devices." src="/data/attachment/portal/201007/ET33814201007230417383.gif" width=604>
  Figure 3. Diagram of the setup for cascading up to 8 MAX11040 devices.
  
  FAULT and OVERFLOW Signals
  The MAX11040 generates active-low OVERFLOW and active-low FAULT signals whenever the input goes above ±0.88% of VREF or above 6V, respectively. This feature is important for generating an alARM height=372 alt="Figure 4. High-frequency analog input OV detection and recovery for a fast-moving input." src="/data/attachment/portal/201007/ET33814201007230417384.gif" width=581>
  Figure 4. High-frequency analog input OV detection and recovery for a fast-moving input.
  
  
  Figure 5. High-frequency analog input OV detection and recovery for a slow-moving input.
  
  Example Data
  The following example data was generated with the MAX11040 EV kit.
  
  Simultaneous Sampling, Programmable Phase Delay, and Cascadable Device Setup
  Figure 6 shows the block diagram of two ADCs. The settings were programmed for various phase delays. An AC signal of 4VP-P running at 120Hz was provided to the 8 inputs (four inputs for each device). The phase delay for each channel was programmed with the following codes:
  
  CH1000µsCH2363646.88µsCH32 × 367293.75µsCH43 × 36108140.62µsCH14 × 36144187.50µsCH25 × 36180234.38µsCH36 × 36216281.25µsCH47 × 36252328.12µs
  
  Figure 6. Two MAX11040 ADCs are shown with the various phase delays applied to the signal.
  
  Figures 7 and 8 show the captured data from the two MAX11040 devices in Figure 6. height=456 alt="Figure 7.The data that resulted from the dual ADC setup in Figure 6." src="/data/attachment/portal/201007/ET33814201007230417387.gif" width=649 border=0>
  More detailed image (PDF, 279KB)
  Figure 7.The data that resulted from the dual ADC setup in Figure 6.
  
  
  More detailed image (PDF, 269KB)
  Figure 8. A zoomed-in view of Figure 7.
  
  Fault and Overflow Detection (Application Assistance)
  If a designer wants to use active-low OVERFLOW or active-low FAULT as interrupt signals, then either an external D flip flop or an internal latch is needed in the hardware. The signals will become latched when the active-low OVERFLOW or active-low FAULT goes low src="/data/attachment/portal/201007/ET33814201007230417389.gif">
  Figure 9. Latching OVERFLOW or FAULT signals.
  
  With all the key features mentioned, MAX11040 is an ideal candidate for:
  Three phase plus neutral lines for power measurement and monitoring
  By using voltage and current transformers to bring down the voltage to acceptable levels, two MAX11040s can be cascaded to monitor three phases plus a neutral voltage and current signals. Although a sigma-delta ADC with 24-bit accuracy, the MAX11040 has sufficient sampling rates to monitor greater than 24 harmonics (industry standard). With ENOB of nearly 18, electrical noise as well as large transients can be captured to help determine the quality of power. Phase shifts that can create offsets in your power-factor calculations can easily be compensated by programming phase delays. At the same time overflow and fault can be easily detected and captured.
  
  
  
  
  EEG/EKG signal monitoring
  
  
  
  With a high dynamic range, a second gain stage can be eliminated to reduce component count and cost, and improve reliability. Having a sigma-delta architecture with a fifth-order modulator, the MAX11040 provides excellent noise performance compared to SAR and other architectures. It also provides 32 channels with phase adjust to monitor many parts of the brain simultaneously.