[讨论]allegro CIS 原理图生成网表时出现元件重复命名的错误怎么

allegro CIS 原理图生成网表时出现元件重复命名的错误怎么办？希望大家帮忙解决一下，谢拉！
以下是 错误显示：
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* Netlisting the design
*
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Design Name:
e:\tpms\PCB\rf pcb.dsn
Netlist Directory:
e:\tpms\pcb\allegro
Configuration File:
F:\Cadence\SPB_15.7\tools\capture\allegro.cfg
Spawning... "F:\Cadence\SPB_15.7\tools\capture\pstswp.exe" -pst -d "e:\tpms\pcb\rf pcb.dsn" -n "e:\tpms\pcb\allegro" -c "F:\Cadence\SPB_15.7\tools\capture\allegro.cfg" -v 3 -j "PCB Footprint"
#1 Warning [ALG0016] Part Name "L_DISC/.350X.175/LS.200X.100/.034_0.75UH" is renamed to "L_DISC/.350X.175/LS.200X.100/.0".
#2 Warning [ALG0016] Part Name "ADTL1-18-75_0_ADTL1-18-75_ADTL1-18-7-1" is renamed to "ADTL1-18-75_0_ADTL1-18-75_ADTL1".
#3 Warning [ALG0016] Part Name "ADTL1-18-75_0_ADTL1-18-75_ADTL1-18-75-2" is renamed to "ADTL1-18-75_0_ADTL1-18-75_ADT_1".
#4 Warning [ALG0016] Part Name "ROS-404-219_ROS-404-219_ROS-404-219" is renamed to "ROS-404-219_ROS-404-219_ROS-404".
#5 Warning [ALG0016] Part Name "HSWA2-30DR_2_HSWA2-30DR_HSWA2-30DR" is renamed to "HSWA2-30DR_2_HSWA2-30DR_HSWA2-3".
Scanning netlist files ...
Loading... e:\tpms\pcb\allegro/pstchip.dat
Loading... e:\tpms\pcb\allegro/pstchip.dat
Loading... e:\tpms\pcb\allegro/pstxprt.dat
Loading... e:\tpms\pcb\allegro/pstxnet.dat
packaging the design view...
Exiting... "F:\Cadence\SPB_15.7\tools\capture\pstswp.exe" -pst -d "e:\tpms\pcb\rf pcb.dsn" -n "e:\tpms\pcb\allegro" -c "F:\Cadence\SPB_15.7\tools\capture\allegro.cfg" -v 3 -j "PCB Footprint"

*** Done ***