把capture cis网表导入allegro出错。。。求救

各位大侠，请教一个菜鸟问题，把capture cis网表导入allegro出错，如下是全部报错信息。网上查到一些方法，没有用。。。pstchip.dat, patxnet.dat, patxprt.dat三个文件都有了。padpath和psmpath都设置过了。。好像是symbol文件找不到？我自己画的元器件的封装，都creat symbol了。。。就是电阻和电容是在capture cis--->property editor中直接填入0603（举例），是不是有一步出错了？？期待答案
Cadence Design Systems, Inc. netrev 15.5 Mon Nov 12 19:43:31 2007
(C) Copyright 2002 Cadence Design Systems, Inc.
------ Directives ------
RIPUP_ETCH FALSE;
RIPUP_SYMBOLS ALWAYS;
MISSING SYMBOL AS ERROR FALSE;
SCHEMATIC_DIRECTORY 'F:/CADENCE/Design';
BOARD_DIRECTORY '';
OLD_BOARD_NAME 'F:/CADENCE/Design/switch-control.brd';
NEW_BOARD_NAME 'F:/CADENCE/Design/switch-control.brd';
CmdLine: netrev -$ -5 -i F:/CADENCE/Design -y 1 F:/CADENCE/Design/#Taaaaaa02508.tmp
------ Preparing to read pst files ------
Starting to read F:/CADENCE/Design/pstchip.dat
Finished reading F:/CADENCE/Design/pstchip.dat (00:00:00.01)
Starting to read F:/CADENCE/Design/pstxprt.dat
Finished reading F:/CADENCE/Design/pstxprt.dat (00:00:00.00)
Starting to read F:/CADENCE/Design/pstxnet.dat
Finished reading F:/CADENCE/Design/pstxnet.dat (00:00:00.01)
------ Oversights/Warnings/Errors ------

illegal character(s)
------ Summary Statistics ------

#1 ERROR(102) Run stopped because errors were detected
netrev run on Nov 12 19:43:31 2007
DESIGN NAME : '通道切换控制板'
PACKAGING ON Jun 17 2005 00:56:10
COMPILE 'logic'
CHECK_PIN_NAMES OFF
CROSS_REFERENCE OFF
FEEDBACK OFF
INCREMENTAL OFF
INTERFACE_TYPE PHYSICAL
MAX_ERRORS 500
MERGE_MINIMUM 5
NET_NAME_CHARS '#%&()*+-./:=>?@[]^_`|'
NET_NAME_LENGTH 24
OVERSIGHTS ON
REPLACE_CHECK OFF
SINGLE_NODE_NETS ON
SPLIT_MINIMUM 0
SUPPRESS 20
WARNINGS ON
1 errors detected
No oversight detected
No warning detected
cpu time 0:00:12
elapsed time 0:00:00