下面是skill的说明，也可以查看il文件：Add assembly reference designators Add assembly rulers Add filled rectangles on etch layer to provide balance during plating process Add pinuse codes from schematic as Allegro properties Allegro to Capture backannotation of pick and place data Align symbols Allows user to add a symbol to the design (For Allegro 14.0) APD - Graphical interface to create the IO connections file used by ZRouter Assign DEVICE_LABEL property to components Build a list of board files Calculate QFP pitch Change Cline Widths /Layer/Width Check component changes between boards Check the status of the dangling line report Check if symbols exist Compare two designs Convert between mils and mm Convert text height in mils to match the database units Copies the 14.x PACKAGE_HEIGHT_MIN/MAX properties to visible text for display and printing Copy Shape to New Class or Subclass Create a list of subclasses for given class Create an Allegro plot Create device files for use with third party netlist implementations Create Thermal Flash Cut Clines By a Graphical Window Selection Cut/Split power rings in APD Package Designs August 2004 Debugging aid which recursively dumps dbid info to a file in hierarchical format Delete unconnected shapes in 8.1 - Source code Delete all vias not on a net June 2005 Delete Signal Integrity FP_* properties from Allegro symbols June 2005 Display all DRC markers for a layer Displays list of DRCs in a design and lets you "walk through" the list Display utility for Datasheets using a URL Display visibility control Distance between 2 pts or from 0,0 Draw targets to line up paper/film plots Etch visibility Extract a netlist in IPC-D-356 format Extract solder paste information Fills class PACKAGE GEOMETRY/BODY_CENTER and draws circle with two diagonals in center of symbol Find all dangling clines and dangling lines Find and identify stubs Find components from list Find components over, under or equal to a user specified height value. Find library path of each Allegro symbol and create a report Find out of date dynamic shapes in 15.0 and later. February 2005 Flare connects into vias and pins Function to determine whether a target point is within a circle GUI to display scripts and replay them with a mouse click Highlight Missing Pin Escapes Skill 8.1 Highlight Missing Test Probes Highlight Nets and Pins without test points SKILL 8.1+ Highlight padstacks from a list of component pin/via padstacks, and a list of drill sizes. Initialize PADPATH variable for the manufacturing class you select Interactive Net List Editor List all rat T points in a design Make a list of all the thermal flashes used in a padstack library Make a list of all slots used in a padstack libraryMarch 2005 Merge Cshapes with pads Mirror text NCLEGEND List all NCLEGEND- subclasses in a design.October 2004 Netlength Report Generator Place DRC markers on Device Pins that are missing a netname Place by List Place symbols and reference designators Print number or point in design db accuracy Redraws one or more objects in a different class with the same coordinates; transforms clines into shapes Remove all externally generated DRCs from the designJuly 2004 Remove fillet properties on clines that are not actually fillets. October 2004 Remove hidden cline and via properties added to fanouts by SPECCTRA Rename reference designators Replace Via padstack by window Replace PACKAGE_HEIGHT_MAX with value of HEIGHT property from ConceptHDL Report short cline segments that are contained within the pad. February 2005 Report the product and version information of the currently running tool. December 2004 Report and highlight pins with the NO_DRC property Report and Log File Viewer Report and highlight single pin nets. February 2005 Show component heights Silkscreen violation checking utility March 2005 Unconnected shape report View DRC locations during shape cleanup after autovoid Workaround for the SKILL axlLineXLine() function which fails for vertical and horizontal segments
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