英特尔布线指南：Sugar Bay and Bromolow-WS

Sugar Bay and Bromolow-WS
Platform Design Guide (PDG)
for use with Sandy Bridge Desktop and UP Workstation Processors and
Cougar Point Platform Controller Hub (PCH)
July 2010
Rev 1.5
Intel Confidential

Contents
1 Introduction............................................................................................................ 25
1.1 Introduction ..................................................................................................... 25
2 Platform Stack-Up and Placement Overview ............................................................ 27
2.1 Introduction ..................................................................................................... 27
2.2 4-Layer Board Stack-Up ..................................................................................... 27
2.3 PCB Technology Considerations ........................................................................... 28
2.3.1 Core Thickness and Material Considerations ............................................... 28
2.3.2 Pads and Vias ........................................................................................ 29
2.4 Minimizing the Effect of Fiber Weave.................................................................... 34
2.4.1 Overview of Fiber Weave......................................................................... 34
2.4.2 Fiber Weave Effect versus Transfer Rate and Trace Length........................... 35
2.4.3 Specific Routing Configurations ................................................................ 36
2.4.4 Offset Routing ....................................................................................... 36
2.4.5 Zig-Zag or Slanted Routing...................................................................... 37
2.4.6 Image Rotation ...................................................................................... 37
2.4.7 Using Alternate PCB Materials .................................................................. 38
2.5 Planes on Outer Layers ...................................................................................... 38
2.6 General Guidelines ............................................................................................ 38
2.6.1 Impedance Requirements by Interface ...................................................... 38
2.6.2 General Routing Guidelines...................................................................... 39
2.6.3 Bends Guidelines.................................................................................... 40
2.6.4 General Differential Layout Guidelines....................................................... 41
2.6.4.1 Breakout Routing Guidelines....................................................... 42
2.6.4.2 Differential Via Usage and Placement Guidelines ........................... 42
2.6.4.3 Differential Length Matching Guidelines........................................ 43
2.6.4.4 Differential Reference Planes Guidelines....................................... 44
2.7 Processor and PCH Component Quadrant Layout ................................................... 45
2.8 Platform Component Keep Out and Placement....................................................... 46
2.9 Manufacturing Considerations ............................................................................. 47
2.10 SO-DIMM requirements...................................................................................... 47
2.10.1 Stackup requirements............................................................................. 47
2.10.2 Connector Assumptions for 1DPC and 2DPC ............................................... 48
2.10.3 Platform component Keep out and placement............................................. 51
2.11 Halogen Frame Retardent Free (HF) recommendations ........................................... 51
3 DDR3 Memory Interface .......................................................................................... 53
3.1 Introduction ..................................................................................................... 53
3.2 UDIMM Guidelines ............................................................................................. 53
3.2.1 Stack-Up Details .................................................................................... 53
3.2.1.1 Planes On Outer Layers (POOL) .................................................. 53
3.2.2 Guideline Terminology ............................................................................ 56
3.2.3 DDR3 UDIMM Layout Design Guidelines..................................................... 57
3.3 SO-DIMM Guidelines .......................................................................................... 65
3.3.1 Stack-Up Details .................................................................................... 65
3.3.2 Guideline Terminology ............................................................................ 65
3.3.3 DDR3 SO-DIMM Layout Design Guidelines ................................................. 66
3.3.4 DDR3 DRAM Reset Routing Recommendation ............................................. 69
3.4 DDR3 DIMM/DRAM Side Reference Voltage ........................................................... 70
4 Processor – PCI Express* and DMI .......................................................................... 73
4.1 PCI Express* and DMI General Routing Guidelines ................................................. 73
英特尔布线指南：Sugar Bay and Bromolow-WS.pdf