[求助]pcb -run drc 发现violation

我用的是DXP 2004 sp2，run drc后，发现很多violation，前辈们帮下：
Protel Design System Design Rule Check
PCB File : \工作\多合一\UNI.PCBDOC
Date : 2009-4-27
Time : 23:54:17
Processing Rule : Hole Size Constraint (Min=0mm) (Max=4mm) (All)
Rule Violations :0
Processing Rule : Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All)
Rule Violations :0
Processing Rule : Width Constraint (Min=0.15mm) (Max=1.27mm) (Preferred=0.3mm) (All)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=0.5mm) (All),(All)
Violation between Via (58.4mm,50.1mm) Top Layer to Bottom Layer and
Arc (59.6648mm,50.5712mm) Top Layer
…………
Violation between Track (59.8mm,48.7858mm)(59.8071mm,48.7929mm) Top Layer and
Pad U1-9(61.3239mm,48.7929mm) Top Layer
……
Violation between Via (57.5mm,36mm) Top Layer to Bottom Layer and
Track (57.5mm,34.7mm)(57.5mm,36mm) Top Layer
……
Violation between Pad Crescent-14(68.5199mm,25.4199mm) Multi-Layer and
Track (67.4801mm,25.4199mm)(68.5199mm,25.4199mm) Top Layer
……
Violation between Via (58.4mm,50.1mm) Top Layer to Bottom Layer and
Track (58.1mm,50.1mm)(58.4mm,50.1mm) Top Layer
……
Violation between Track (80.264mm,11.176mm)(80.276mm,11.176mm) Top Layer and
Track (47.5239mm,11.176mm)(80.264mm,11.176mm) Top Layer
……
Violation between Track (58.6mm,50.1mm)(69.4mm,50.1mm) Bottom Layer and
Arc (58.6992mm,50.5712mm) Bottom Layer
……
Violation between Via (58.4mm,50.1mm) Top Layer to Bottom Layer and
Arc (58.6992mm,50.5712mm) Bottom Layer

……
Violation between Polygon Region (0 hole(s)) Bottom Layer and
Track (91.2mm,38.3mm)(93.0401mm,36.4599mm) Bottom Layer
Violation between Track (84.9mm,51.7mm)(92mm,44.6mm) Bottom Layer and
Track (91.2mm,38.3mm)(91.2mm,44.3mm) Bottom Layer
……
Violation between Pad 1000U-1(40.9999mm,35.7mm) Multi-Layer and
Track (42.0979mm,34.798mm)(44.196mm,34.798mm) Bottom Layer
Violation between Pad 1000U-2(42.9999mm,35.7mm) Multi-Layer and
Track (42.0979mm,34.798mm)(44.196mm,34.798mm) Bottom Layer
Violation between Via (80.2998mm,5.7099mm) Top Layer to Bottom Layer and
Track (75.8139mm,5.7099mm)(84.1959mm,5.7099mm) Bottom Layer
……
Violation between Pad 1000U-8(42.9999mm,29.7mm) Multi-Layer and
Polygon Region (0 hole(s)) Bottom Layer
……
Violation between Pad 1000U-1(40.9999mm,35.7mm) Multi-Layer and
Polygon Region (55 hole(s)) Bottom Layer
Rule Violations :405
Processing Rule : Broken-Net Constraint ( (All) )
Rule Violations :0
Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All)
Violation between Via (57.5mm,36mm) Top Layer to Bottom Layer and
Track (57.5mm,34.7mm)(57.5mm,36mm) Top Layer
Violation between Track (67.4801mm,25.4199mm)(68.5199mm,25.4199mm) Top Layer and
Track (66.7801mm,25.4199mm)(67.4801mm,25.4199mm) Top Layer
Violation between Pad Crescent-14(68.5199mm,25.4199mm) Multi-Layer and
Track (67.4801mm,25.4199mm)(68.5199mm,25.4199mm) Top Layer
……
Violation between Via (80.2998mm,5.7099mm) Top Layer to Bottom Layer and
Arc (76.8109mm,3.1071mm) Bottom Layer
……
Violation between Track (92.1998mm,40.2mm)(93.1999mm,39.1999mm) Bottom Layer and
Track (92mm,40.2mm)(92.1998mm,40.2mm) Bottom Layer
Violation between Via (58.3mm,48.8mm) Top Layer to Bottom Layer and
Track (58.3mm,48.8mm)(58.9456mm,49.4456mm) Bottom Layer
Rule Violations :95
More than 500 violations detected. DRC stopped!
Violations Detected : 501
Time Elapsed : 00:00:00