关于VHDL的loadable shift register

各位大大，这是我写的vhdl，不知道中间哪错了，用modelsim simulate到140ns的时候就停住了。


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4. library ieee;
5. use ieee.std_logic_1164.all;
7. entity loadable_shift_register is
8. generic(
9. DATA_WIDTH : natural := 12);
10. port(
11. data_in : in std_logic_vector(DATA_WIDTH-1 downto 0);
12. ld : in std_logic;
13. clk : in std_logic;
14. rsh : in std_logic;
15. rst_L : in std_logic;
16. data_out: out std_logic_vector(DATA_WIDTH-1 downto 0));
17. end entity loadable_shift_register;
19. architecture bhv of loadable_shift_register is
20. begin
21. process (clk, rst_L, ld, data_in, rsh)
22. variable data : std_logic_vector(DATA_WIDTH-1 downto 0);
23. begin
25. if rst_L = '0' then
26. data := (others => '0');
27. elsif clk'event and clk = '1' then
28. if rsh = '1' then
29. for i in 0 to (DATA_WIDTH-1) loop
30. data(i) := data(i+1);
31. end loop;
32. data(DATA_WIDTH-1) := '0';
33. elsif ld = '1' then
34. data := data_in;
35. end if;
36. else
37. data := data;
39. end if;
42. data_out <= data;
44. end process;
46. end architecture bhv;
50. -------------------------------------------------------------------------------
51. -- TEST BENCH FOR LOADABLE SHIFT REGISTER
52. -------------------------------------------------------------------------------
54. library ieee;
55. use ieee.std_logic_1164.all;
57. entity loadable_shift_register_tben is
58. end loadable_shift_register_tben;
60. architecture tben of loadable_shift_register_tben is
62. component loadable_shift_register
63. generic (
64. DATA_WIDTH : natural);
65. port (
66. data_in : in std_logic_vector(DATA_WIDTH-1 downto 0);
67. ld : in std_logic;
68. rsh : in std_logic;
69. clk : in std_logic;
70. rst_L : in std_logic;
71. data_out : out std_logic_vector(DATA_WIDTH-1 downto 0));
72. end component;
74. signal data_in : std_logic_vector(11 downto 0) := "000000000000";
75. signal ld : std_logic := '0';
76. signal rsh : std_logic := '0';
77. signal clk : std_logic := '0';
78. signal rst_L : std_logic := '0';
79. signal data_out : std_logic_vector(11 downto 0);
81. begin -- tben
83. -- Instantiation of device under test
84. DUT : loadable_shift_register
85. generic map (DATA_WIDTH => 12)
86. port map (data_in => data_in,
87. ld => ld,
88. rsh => rsh,
89. clk => clk,
90. rst_L => rst_L,
91. data_out => data_out);
93. -- DUT stimulus
95. -- generates a periodic clock with T_clk = 40 ns
96. process
97. begin -- process clk_gen
98. wait for 20 ns;
99. clk <= not(clk);
100. end process;
102. -- models the reset signal (starts at '0')
103. rst_L <= '1' after 15 ns;
105. -- models the signals data_in, ld and rsh for each period of clk
106. process (clk, rst_L)
107. variable clk_ticks : natural := 0; -- keeps track of number of clk ticks
108. begin -- process
109. if rst_L = '0' then -- asynchronous reset (active low)
110. clk_ticks := 0;
111. data_in <= "000000000000" after 5 ns;
112. ld <= '0' after 5 ns;
113. rsh <= '0' after 5 ns;
114. elsif clk'event and clk = '1' then -- rising clock edge
115. clk_ticks := clk_ticks+1;
116. if clk_ticks = 1 then
117. data_in <= "000011110000" after 5 ns;
118. ld <= '1' after 5 ns;
119. rsh <= '0' after 5 ns;
120. elsif clk_ticks = 2 then
121. data_in <= "111111111111" after 5 ns;
122. ld <= '0' after 5 ns;
123. rsh <= '0' after 5 ns;
124. elsif clk_ticks = 3 then
125. data_in <= "111111111111" after 5 ns;
126. ld <= '0' after 5 ns;
127. rsh <= '1' after 5 ns;
128. elsif clk_ticks = 4 then
129. data_in <= "111111111111" after 5 ns;
130. ld <= '1' after 5 ns;
131. rsh <= '1' after 5 ns;
132. elsif clk_ticks = 5 then
133. data_in <= "111111111111" after 5 ns;
134. ld <= '1' after 5 ns;
135. rsh <= '0' after 5 ns;
136. else
137. data_in <= "XXXXXXXXXXXX" after 5 ns;
138. ld <= '0' after 5 ns;
139. rsh <= '0' after 5 ns;
140. end if;
141. end if;
142. end process;
144. end tben;

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