发一篇设计内容非常全乎的关于全差分运放设计的论文
发一篇关于一个全差分运放设计的论文（共105页），所设计内容非常全乎！包括运放十多项指标的定义及其各项指标（SR，PSRR，Noise等等）的分析与设计实现，CMFB设计，稳定性补偿，谐波抑制，版图设计，电路仿真分析，工艺变化与不匹配问题等等。Table of contents:1. Introduction ................................................................................................................................81.1 Introduction ...............................................................................................................................81.1.1 General considerations...........................................................................................................81.1.2 ADC Definition and characterization ....................................................................................91.2 The use of operational amplifier in ADC topology...................................................................91.3 The need of high specifications...............................................................................................102. Specifications........................................................................................................................... 112.1. Signal to Noise Ratio (SNR) definition..................................................................................112.2 Signal Distortion to Noise Ratio (SNDR) definition.............................................................122.3 Power Supply Rejection Ratio (PSRR) definition..................................................................122.4 Common Mode Rejection Ratio (CMRR) definition..............................................................122.5 Power dissipation....................................................................................................................132.6 Slew rate.................................................................................................................................132.7 Settling time............................................................................................................................142.8 Noise.......................................................................................................................................142.8.1 Thermal noise........................................................................................................................152.8.2 1/f (flicker) noise...................................................................................................................152.9 Spurious free dynamic range...................................................................................................162.10 Open loop DC gain.................................................................................................................163. Theoretical approach of operational amplifier..........................................................................183.1. Simple single ended operational amplifier.............................................................................183.2. Full differential operational amplifier.....................................................................................203.2.1 General topology..................................................................................................................213.2.2 Common mode feedback (CMFB) topology.......................................................................213.2.2.1 Understanding the need of CMFB....................................................................................213.2.2.2 Continuous time CMFB....................................................................................................233.2.2.3 Sensing structure...............................................................................................................243.2.2.4 Comparator design.............................................................................................................263.2.2.5 Switched capacitor CMFB................................................................................................273.2.2.6 Switch care.........................................................................................................................293.2.2.6.1 Dummy switch................................................................................................................303.2.2.6.2 Complementary switch...................................................................................................303.2.3 Slew rate..............................................................................................................................303.3 Folded cascode structure........................................................................................................313.3.1 Topology description............................................................................................................313.3.2 Gain calculation....................................................................................................................323.4 Telescopic structure.................................................................................................................343.4.1 Noise consideration..............................................................................................................353.4.2 Gain boosting.......................................................................................................................373.5 Two stage topology.................................................................................................................393.5.1 Miller compensation.............................................................................................................393.5.2 Zero pole compensation.......................................................................................................423.5.3 Noise consideration..............................................................................................................433.6 Conclusion and choice.............................................................................................................443.6.1 Overall topology choice: 2 stage op amp.............................................................................443.6.2 Compensation method..........................................................................................................453.6.3 Common Mode Feedback choice.........................................................................................464.Implementation..........................................................................................................................474.1. Schematic and simulations.....................................................................................................474.1.1. Input stage..........................................................................................................................474.1.1.1 NMOS input transistor......................................................................................................474.1.2. Gain boosting.......................................................................................................................494.1.3. Output stage........................................................................................................................504.1.4. Common mode feedback (CMFB) circuit...........................................................................514.1.4.1 CMFB compensation network..........................................................................................514.1.5. Compensation.....................................................................................................................534.1.6. Overall topology and simulations.......................................................................................544.1.7 Spectral
analyze...................................................................................................................564.1.7.1 Spurious Free Dynamic Range.........................................................................................564.1.7.2 Third harmonic rejection and output dynamic range.........................................................574.1.8 Slew rate..............................................................................................................................584.1.9. Power Supply Rejection Ratio (PSRR)...............................................................................584.1.10 Noise analyse results...........................................................................................................594.2. Layout....................................................................................................................................614.2.1. Layout considerations.........................................................................................................624.2.1.1. Common centroide structure............................................................................................624.2.1.1.1 One dimension approach................................................................................................624.2.1.1.2 Two dimensional common centroide structure..............................................................634.2.1.2. Gate shadowing limitation...............................................................................................644.2.1.2.1 Source of the gate shadowing problem..........................................................................644.2.1.3. Dummy structure..............................................................................................................644.2.1.4. Rooting care......................................................................................................................664.2.1.4.1 Dummy lines...................................................................................................................664.2.1.4.2 Contact size and layers width.......................................................................................674.2.1.5. Minimum gate finger number...........................................................................................684.2.2. Actual layout........................................................................................................................684.2.2.1 Input stage.........................................................................................................................684.2.2.2 Output stage......................................................................................................................704.2.2.3. Overall layout of the operational amplifier......................................................................714.3 Layout Versus Schematic (LVS)...........................................................................................714.4. Post layout simulation............................................................................................................744.4.1. Worst case simulation.........................................................................................................754.4.1.1 Worst Power simulation....................................................................................................774.4.1.2. Worst Speed simulation...................................................................................................774.4.1.3 Worst Zero simulation......................................................................................................784.4.2 Other model..........................................................................................................................784.4.3. Monte Carlo simulations.....................................................................................................784.4.3.1. Process variations............................................................................................................804.4.3.2. Mismatch variations.........................................................................................................804.4.3.3 Process and mismatch variations.....................................................................................825. Conclusion and outlook..............................................................................................................86
附件
Design of an integrated full differential operational amplifier.pdf (2.02 MB)
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